A laptop does not switch on in one step. Rails come up in a strict order, each one enabled by a signal and each one confirmed by a power-good report before the next stage starts. The power sequence page in the schematic draws that order. Once you can read it, a no-power fault becomes a question of finding the first step that did not happen.
What the power sequence page looks like
Most ODM schematics include one or two pages near the beginning titled "Power Sequence", "Power On Sequence" or "Timing Diagram". You will find one of two styles, sometimes both:
- A timing chart — horizontal lines for each rail and signal, stepping up from low to high in order, with arrows showing which event triggers the next.
- A flow chart or table — numbered steps such as "1. Adapter in → +3VALW, +5VALW", "2. EC_ON high", "3. RSMRST# high", with the signal names and delays.
Both carry the same information: what turns on, in what order, and what triggers each step.
The stages in a typical Intel laptop
Names vary between ODMs and platforms, and AMD boards use different signal names for similar steps, but the stages are broadly the same. Read your own schematic for the exact order.
| Stage | What happens | Signals and rails to look for |
|---|---|---|
| 0. Coin cell only (G3) | RTC well powered from the coin cell | +RTCVCC, RTCRST# |
| 1. Power applied | Adapter or battery reaches the charger and system rail | DCIN, ACIN/ACOK, B+ |
| 2. Always-on rails | 3.3 V and 5 V standby regulators start | +3VALW, +5VALW, +3V_S5 |
| 3. EC starts | EC runs from the always-on rail, keeps it enabled, reads the button | EC_ON, EC_RST# |
| 4. Standby ready | EC or a sequencer releases the PCH from resume reset | RSMRST#, DSW_PWROK |
| 5. Button press | EC sees the button and toggles the PCH power button input | NBSWON#, PWRBTN# |
| 6. Leaving S5/S4 | PCH releases its sleep signals | SLP_S5#, SLP_S4# (SUSC#) |
| 7. Memory rails | Memory power comes up for S3 and S0 | +1.2V, +0.6VS, SYSON |
| 8. Leaving S3 | PCH releases SLP_S3#, system rails switch on | SLP_S3# (SUSB#), SUSP#, +3VS, +5VS |
| 9. CPU power | Core regulator enabled, ramps up, reports power good | VR_ON, +VCORE, VR_PWRGD |
| 10. Platform ready | Power-good signals reach the PCH and CPU | PCH_PWROK, SYS_PWROK |
| 11. Reset released | PCH releases platform reset; the BIOS starts running | PLTRST# |
Turning the chart into a checklist
The sequence page is most useful as a list of measurements. With the battery disconnected and the adapter (or a bench supply) connected:
- Measure the input and system rail. If they are missing, the fault is in the input protection or charger area.
- Measure the always-on rails. Missing always-on rails with a good system rail point at their regulator, its enable or a short on the rail.
- Check the EC's supply and reset. The EC needs its always-on rail and usually a crystal or internal oscillator.
- Measure the resume reset signal. If
RSMRST#stays low, the PCH will ignore the power button. Find what drives it on your board. - Press the button and watch the sleep signals.
SLP_S4#andSLP_S3#going high show that the PCH responded. - Measure memory rails, then system rails, then the core rail.
- Check the power-good signals and platform reset. A board with every rail present but
PLTRST#stuck low is waiting for a power-good that never came.
The first measurement that fails is your starting point. Everything after it is a consequence, not a cause.
How enable and power-good signals connect the stages
Each stage is usually started by an enable signal and confirmed by a power-good signal. The enable might come from the EC, the PCH or from the power-good of the previous regulator. When a rail is missing, check in this order:
- Does the regulator have its input voltage?
- Is its enable pin high?
- Is there a short on its output?
- Is the regulator itself working (switching node activity, feedback, bootstrap)?
When a rail is present but the next stage does not start, check the power-good output of that rail's regulator. The details of both kinds of signal are in Enable Signals in Laptop Power Sequencing and Power Good Signals and Why They Matter.
Common surprises when following the sequence
- Rails that are supposed to be off. In S5 the system rails (
+3VS,+5VS) and the core rail should be absent. That is normal, not a fault. - Rails that pulse. Some boards try to start, fail, shut down and retry. You see a rail appear for a moment and disappear. Watch with an oscilloscope, or with a meter that has a min/max function.
- Steps handled by the EC. On many boards the EC sits between the PCH and the regulators, so a missing enable may be the EC's decision — for example because it sees no battery, a bad adapter ID or a stuck button.
- Different names on the same signal.
SLP_S3#from the PCH may becomeSUSB#at the EC andSUSP#after an inverter. The net naming guide explains these renames.
AMD boards: same idea, different names
AMD laptops follow the same staged logic — standby rails, a resume reset, a button event, sleep signals, then memory, system and core rails — but the names in the schematic differ. Active-low signals are often written with an _L suffix (RSMRST_L, PWR_BTN_L, SLP_S3_L, SLP_S5_L), the controller hub functions sit in the processor package rather than a separate chip, and the CPU core and SoC rails are usually supplied by one dual-output controller with its own power-good. The EC still sits in the middle, so the checklist above applies with the names translated.
The safest approach is to build the sequence from the schematic you have, not from memory of another platform. Note each regulator, its enable source and where its power-good goes, then compare that order with what you measure.
Without a sequence page
Some schematics do not include a sequence chart. You can rebuild it from the power section: for each regulator, note its input, its enable source and its power-good destination. Draw arrows from each power-good to the enable it feeds. The resulting chain is the power sequencing of your board.
Platform design guides from Intel and AMD also describe the general order, though the board-specific signals come only from the schematic.
FAQ
Is the power sequence the same on every laptop?
The broad order is similar on boards of the same platform, because it follows the processor vendor's requirements. Signal names, which chip drives each enable, and the role of the EC vary between ODMs and boards.
What should I measure first on a dead board?
The input and system rail, then the always-on rails. Most no-power faults are found in the first three stages. A full walk-through is in Laptop Not Turning On: Step-by-Step Motherboard Diagnosis.
Why do all rails come up but the laptop still does not boot?
Then the problem is usually after the power sequence: a missing power-good, platform reset held low, a corrupted BIOS, memory or CPU issues. Check the last stages of the chart first.
Can I trigger a stage manually?
Experienced repairers sometimes pull an enable signal high to test a regulator, but doing it on the wrong pin or with the wrong voltage can damage chips. Only do it when the schematic makes the enable logic clear and you know the safe level.
Bottom line
Read the power sequence page as an ordered list of measurements. Work through it from the input to the platform reset and stop at the first thing that does not happen; that is where the fault is, and the enable and power-good signals around it tell you why.